This application claims priority to an application entitled xe2x80x9cSemiconductor Memory Device and Manufacturing Method Thereofxe2x80x9d filed in the Korean Industrial Property Office on Jan. 20, 2000, and assigned Ser. No. 2000-3625, the contents of which are hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device and to a method of manufacturing the same. More particularly, the present invention relates to a semiconductor memory device and a method of manufacturing the same wherein the level of integration is increased and a resistor device maintains sufficient length.
2. Description of the Related Art
Semiconductor devices are largely divided into two categories: a volatile memory RAM (Random Access Memory) and a nonvolatile memory ROM (Read Only Memory). In a DRAM (Dynamic Random Access Memory), a variation of a RAM, a unit cell is comprised of one access transistor and one capacitor. A DRAM additionally includes a memory cell area where a plurality of memory cells are regularly arranged in X and Y directions and a peripheral circuit area formed near the cell array area to drive and control the memory cells. These memory cells are driven by selecting a column signal line, called a word line, and a row signal line, called a bit line. Various devices are formed in the peripheral circuit area such as transistors, diodes, and resistor devices. A conductive layer or a transistor is used as a resistor device.
In conventional technology, when a polysilicon gate is used, it is used as a resistor device using a metal contact or a bit line contact. Since a polycide gate stacked with polysilicon and a metal silicide was used to reduce the resistance of the gate, the low unit sheet resistance of the gate renders the gate unsuitable for a resistor device. Therefore, a polysilicon plate electrode of a capacitor is currently used as a resistor device.
FIG. 1 is a sectional view illustrating a cell array area and a peripheral circuit area in a conventional DRAM device known in the prior art.
Referring initially to FIG. 1, a gate area, including a gate insulation layer (not shown), a polysilicon layer 14, a metal silicide film 16 and a spacer insulation layer 18, is formed in the memory cell array area of a semiconductor substrate 10 having an active region and a field region defined thereon by a field oxide film 12. Impurity diffusion regions (not shown) are formed at both sides of the gate area to act as source/drain regions of a transistor, thereby completing an access transistor.
After landing pads 20 and 21 are formed between gate areas, a first interlayer insulation layer 22 is formed by depositing an oxide film, for example. An opening is formed to expose the landing pad 20 in contact with the drain region of the access transistor by photolithography. Then, a bit line is formed by sequentially depositing a polysilicon layer 24, a tungsten silicide 26, and an anti-reflection layer 28.
A second interlayer insulation layer 30 is formed by depositing an oxide film on the resultant structure. Then, an opening is formed to expose the landing pad 21 in contact with the source region of the access transistor. A capacitor is formed by sequentially depositing a hemispherical silicon layer 32 as a lower electrode, an ONO (Oxide-Nitride-Oxide) dielectric layer 34 having a high dielectric constant, and a polysilicon layer 36a as an upper electrode on the resultant structure having the opening. Here, a resistor device 36b having a length A is formed by remaining the polysilicon layer for the upper electrode of the capacitor in the peripheral circuit area. Next, a third interlayer insulation layer 38 is formed by depositing an oxide film on the overall surface of the resultant structure.
As described above, the polysilicon layer that acts as the upper electrode of a capacitor remains in the peripheral circuit area to be used as a resistor device in the conventional technology. The resistor device should have the greatest possible length with respect to the minimum available area to achieve a high resistance necessary for circuit operation, however, this reduces process margin in a subsequent photolithography step for forming a metal connection line. Furthermore, the increased resistor device length increases unit circuit area, which in turn increases the total chip area.
It is, therefore, a feature of an embodiment of the present invention to provide a semiconductor memory device and a method of manufacturing the same that can increase the level of integration by minimizing the length of a resistor device.
It is another feature of an embodiment of the present invention to provide a semiconductor memory device and a method of manufacturing the same that can ensure a subsequent process margin.
It is an additional feature of an embodiment of the present invention to provide a semiconductor memory device and a method of manufacturing the same that can increase a level of integration, thereby ensuring high resistance required for circuit operation.
The above features can be achieved by providing a method of manufacturing a semiconductor memory device, wherein landing pads are formed to contact a source/drain region of an access transistor in a memory cell array area and a first resistor device is formed in the peripheral circuit area, by depositing a first conductive layer on a semiconductor substrate having an access transistor formed thereon and patterning the first conductive layer. Then, an interlayer insulation layer is formed on the resultant structure and a lower electrode and a dielectric layer having a high dielectric constant of a capacitor are formed to contact the source/drain region of the access transistor. By depositing a second conductive layer on the resultant structure having the dielectric layer and patterning the dielectric layer, a capacitor upper electrode is formed in the memory cell array area and a second resistor device is formed in the peripheral circuit area.
Preferably, the first and second conductive layers are polysilicon layers. It is also preferable that the first and second resistor devices are spaced by a predetermined distance in a horizontal direction.
According to another aspect of an embodiment of the present invention, there is provided a semiconductor memory device having a memory cell array area and a peripheral circuit area. In the semiconductor memory device, a first resistor device is formed in the peripheral circuit area when a landing pad is formed to contact an impurity diffusion region of an access transistor in the memory cell array area. A second resistor device is formed in the peripheral circuit area when a capacitor upper electrode is formed in the memory cell array area.
These and other features of the present invention will be readily apparent to those skilled in the art upon review of the detailed description of the preferred embodiments that follows.